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sy89465u precision lvds 1:10 fanout with 2:1 runt pulse eliminator mux and internal termination precision edge is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 general description the sy89465u is a low-jitter, 1:10 lvds fanout buffer with a 2:1 differential input multiplexer (mux) optimized for redundant source switchover applications. unlike standard multiplexers, the sy89465us 2:1 runt pulse eliminator (rpe) mux prevents any short cycles or ?runt? pulses during switchover. in addition, a unique fail-safe input (fsi) protection prevents metastable conditions when the selected input cloc k fails to a dc voltage (voltage between the pins of the differential input drops below 100mv). the differential input includes micrel?s, 3-pin internal termination architecture that allows customers to interface to any differential signal (ac- or dc- coupled) as small as 100mv (200mv pp ) without any level shifting or termination resistor networks in the signal path. the outputs are lvds-compatible with fast rise/fall times guaranteed to be less than 220ps. the sy89465u operates from a 2.5v 5% supply and is guaranteed over the full industrial temperature range of ?40c to +85c. the sy89465u is part of micrel?s high-speed, precision edge ? product line. all support documentation can be found on micrel?s web site at: www.micrel.com . precision edge ? features ? selects between two sources, and provides 10 precision lvds copies ? guaranteed ac performance over temperature and supply voltage: ? wide operating frequency: 1khz to >1.5ghz ? <1200ps in-to-out t pd ? <220ps t r /t f ? unique, patent-pending input isolation design minimizes adjacent channel crosstalk ? fail-safe input prevents oscillations ? ultra-low jitter design: ? 183 fs rms phase jitter (typical) ? <0.7ps rms mux crosstalk-induced jitter ? unique patented input termination and vt pin accepts dc- and ac-coupled inputs (cml, pecl, lvds) ? 325mv lvds output swing ? 2.5v 5% supply voltage ? ? 40c to +85c industrial temperature range ? output enable ? available in 44-pin (7mm x 7mm) qfn package applications ? redundant clock switchover ? fail-safe clock protection markets ? lan/wan ? enterprise servers ? ate ? test and measurement
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 2 typical application simplified example illustrating runt pulse e liminator (rpe) when primary clock fails ordering information part number package type operating range package marking lead finish SY89465UMY qfn-44 industrial sy89465u with pb-free bar-line indicator matte-sn pb-free SY89465UMYtr (2) qfn-44 industrial sy89465u with pb-free bar-line indicator matte-sn pb-free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel.
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 3 pin configuration 44-pin qfn pin description pin number pin name pin function 2, 5, 7, 10 in0, /in0 in1, /in1 differential inputs: these input pairs are the differential signal inputs to the device. these inputs accept ac- or dc-coupled signals as small as 100mv (200mv pp ). each pin of a pair internally terminates to a v t pin through 50 ? . please refer to the ?input interface applications? section for more details. 4, 9 vref-ac0 vref-ac1 reference voltage: these outputs bias to v cc ?1.2v. they are used for ac-coupling inputs in and /in. connect v ref-ac directly to the corresponding v t pin. bypass with 0.01f low esr capacitor to v cc . due to the limited drive capability, the v ref-ac pin is only intended to drive its respective v t pin. maximum sink/source current is 1.5ma. please refer to the ?input interfac e applications? section for more details. 3, 8 vt0, vt1 input termination center-tap: each side of t he differential input pair terminates to a v t pin. the v t0 and v t1 pins provide a center-tap to a termination network for maximum interface flexibility. please refer to the ?input interface applications? section for more details. 13, 15, 22, 23 28, 33, 34, 41, 43, 44 vcc positive power supply: bypass with 0.1f||0.01f low-esr capacitors as close to the v cc pins as possible. 39, 40 37, 38 35, 36 31, 32 29, 30 26, 27 24, 25 20, 21 18, 19 16, 17 /q0, q0 /q1, q1 /q2, q2 /q3, q3 /q4, q4 /q5, q5 /q6, q6 /q7, q7 /q8, q8 /q9, q9 differential outputs: these di fferential lvds outputs are a logic function of the in0, in1, and sel inputs. please refer to the ?truth table? below for details.
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 4 pin description (continued) pin number pin name pin function 42 sel this single-ended ttl/cmos-compatible inpu t selects the inputs to the multiplexer. note that this input is internally connected to a 25k ? pull-up resistor and will default to logic high state if left open. v th = v cc /2. 1, 11, 6 gnd, exposed pad ground: ground and exposed pad must be conn ected to the same ground plane. 12 cap power-on-reset (por) initialization capacitor. when using the multiplexer with rpe capability, this pin is tied to a capacitor to v cc . the purpose is to ensure the internal rpe logic starts up in a known state. see ?power-on reset (por) description? section for more details regarding capacitor se lection. if this pin is tied directly to v cc , the rpe function will be disabled and the multiplexer will function as a normal multiplexer. the cap pin should never be left open or tied directly to gnd. 14 en single-ended input: this ttl/cmos input disables and enables the q0-q9 outputs. it is internally connected to a 25k ? pull-up resistor and will default to a logic high state if left open. when disabled, clk output goes low and /clk goes high. en being synchronous, outputs will be enabled/di sabled when they are in low state. thus, a runt pulse is avoided if the devic e is enabled/disabled by an asynchronous control. v th = v cc /2. truth table inputs outputs in0 /in0 in1 /in1 sel q /q 0 1 x x 0 0 1 1 0 x x 0 1 0 x x 0 1 1 0 1 x x 1 0 1 1 0
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 5 absolute maximum ratings (1) supply voltage (v cc ) ..........................?0.5v to +4.0v input voltage (v in ) ..................................?0.5v to v cc input current (i in ) ........................................................ source/sink current on in, /in ................ 50ma source/sink current on v t ..................... 100ma v ref-ac current source/sink current on v ref-ac .................. 2ma lead temperature (soldering, 20 sec.) ..........+260c storage temperature (t s )..................?65c to 150c operating ratings (2) supply voltage (v cc ).................. +2.375v to +2.625v ambient temperature (t a )................ ?40c to +85c package thermal resistance (3) qfn ( ja ) still-air .................................................. 24.4c/w qfn ( jb ) junction-to-b oard ................................... 8. 1c/w dc electrical characteristics (4) t a = ?40c to +85c, unless otherwise stated. symbol parameter condition min. typ. max. units v cc power supply 2.375 2.5 2.625 v i cc power supply current no load, max v cc 250 325 ma r in input resistance (in-to-v t ) 45 50 55 ? r diff_in differential input resistance (in-to-/in) 90 100 110 ? v ih input high voltage (in, /in) 1.2 v cc v v il input low voltage (in, /in) 0 v ih ? 0.1 v v in input voltage swing (in, /in) s ee figure 1a (note 5) 0.1 2.5 v v diff_in differential input voltage swing |in-/in| see figure 1b 0.2 v v in_fsi input voltage threshold that triggers fsi 30 100 mv v t_in in-to-v t (in, /in) 1.28 v v ref-ac output reference voltage v cc ? 1.3 v cc ? 1.2 v cc ? 1.1 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional oper ation is not implied at conditions other than thos e detailed in the operational sections of this data sheet. exposure to absolute maximu m rating conditions for extended periods ma y affect device reliability. 2. the data sheet limits are not guaranteed if t he device is operated beyond the operating ratings. 3. package thermal resistance assumes exposed pad is soldered (o r equivalent) to the devices most negative potential on the pcb . ja and jb values are determined for a 4-layer board in still air unless otherwise stated. 4. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d. 5. v in (max) is specified when v t is floating.
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 6 lvds outputs dc electrical characteristics (6) v cc = 2.5v 5%; r l = 100 ? across output pair or equivalent; t a = ?40c to + 85c, unless otherwise stated. symbol parameter condition min. typ. max. units v ocm output common mode voltage 1.125 1.275 v v ocm change in vocm between complementing output states ?50 +50 mv v out output voltage swing see figure 1a. 250 325 mv v diff-out differential output voltage swing see figure 1b. 500 650 mv lvttl/cmos dc electri cal characteristics (6) v cc = 2.5v 5%; t a = ?40c to + 85c, unless otherwise stated. symbol parameter condition min. typ. max. units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current -125 30 a i il input low current -300 a note: 6. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d.
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 7 ac electrical characteristics (7) v cc = 2.5v 5%; r l = 100 ? across the output pair; t a = ?40c to + 85c, unless otherwise stated. symbol parameter condition min. typ. max. units f max maximum operating frequency v out 200mv, clock 1.5 2.0 ghz differential propagation delay in-to-q 100mv < v in 200mv (8) 550 800 1200 in-to-q 200mv < v in 800mv (8) 500 700 1100 ps sel-to-q rpe enabled, see timing diagram 17 cycles t pd sel-to-q rpe disabled (v sel = v cc /2) 600 1200 ps t pd tempco differential propagation delay temperature coefficient 500 fs/ o c t s en set-up time en-to-clk note 9 0 ps t h en hold time clk-to-en note 9 650 ps output-to-output skew note 10 5 25 t skew part-to-part skew note 11 300 ps rms phase jitter output: 622mhz integration range: 12khz ? 20mhz 183 fs t jitter crosstalk-induced jitter note 12 0.7 ps rms t r, t f output rise/fall time (20% to 80% ) at full output swing. 70 120 220 ps notes: 7. high-frequency ac-parameters are guar anteed by design and characterization. 8. propagation delay is measured with input t r , t f 300ps (20% to 80%) and v il 800mv. the propagation delay is function of the rise and fall times at in. see ?typical oper ating characteristics? for details. 9. set-up and hold times apply to synchronous applications that in tend to enable/disable before the next clock cycle. for async hronous applications, set-up and hold do not apply. 10. output-to-output skew is measured between tw o different outputs under identical transitions. 11. part-to-part skew is defined for two parts with identical pow er supply voltages at the same temperature and with no skew of the edges at the respective inputs. 12. crosstalk is measured at the output while applying two sim ilar differential clock frequencies that are asynchronous with re spect to each other at the inputs.
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 8 phase noise graph
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 9 functional description rpe mux and fail-safe input the sy89465u is optimized for clock switchover applications where switching from one clock to another clock without runt pulses (short cycles) is required. it features two unique circuits: runt-pulse eliminator (rpe) circuit the rpe mux provides a ?glitchless? switchover between two clocks and prevents any runt pulses from occurring during the switchover transition. the design of both clock inputs is identical (i.e., the switchover sequence and protection is symmetrical for both input pairs, in0 or in1. thus, either input pair may be defined as the primary input). if not required, the rpe function can be permanently disabled to allow the switchover between inputs to occur immediately. if the cap pin is tied directly to v cc , the rpe function will be disabled and the multiplexer will function as a normal multiplexer. fail-safe input (fsi) circuit the fsi function provides protection against a selected input pair that drops below the minimum amplitude requirement. if the selected input pair drops sufficiently below the 100mv minimum single- ended input amplitude limit (v in ), or 200mv differentially (v diff_in ), the output will latch to the last valid clock state. rpe and fsi functionality the basic operation of the rpe mux and fsi functionality is described with the following four case descriptions. all descriptions are related to the true inputs and outputs. the primary (or selected) clock is called clk1; the secondary (or alternate) clock is called clk2. due to the totally asynchronous relation of the in and sel signals and an additional internal protection agains t metastability, the number of pulses required for the operations described in cases 1-4 can vary within certain limits. refer to ?timing diagrams? section for detailed information. case #1: two normal clocks and rpe enabled in this case, the frequency difference between the two running clocks, in0 and in1, must not be greater than 1.5:1. for example, if the in0 clock is 500mhz, the in1 clock must be within the range of 334mhz to 750mhz. if the sel input changes state to select the alternate clock, the switchov er from clk1 to clk2 will occur in three stages. ? stage 1: the output will continue to follow clk1 for a limited number of pulses. ? stage 2: the output will remain low for a limited number of pulses of clk2. ? stage 3: the output follows clk2. timing diagram 1
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 10 case #2: input clock failure: switching from a selected clock stuck high to a valid clock (rpe enabled). if clk1 fails high befo re the rpe mux selects clk2 (using the sel pin), the switchover will occur in three stages. ? stage 1: the output will remain high for a limited number of pulses of clk2. ? stage 2: the output will switch to low and then remain low for a limited number of falling edges of clk2. ? stage 3: the output will follow clk2. timing diagram 2 note: output shows extended clock cycle during switchover. pulse wi dth for both high and low of this cycle will always be greater than 50% of the clk2 period.
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 11 case #3: input clock failure: switching from a selected clock stuck low to a valid clock (rpe- enabled). if clk1 fails low before the rpe mux selects clk2 (using the sel pin), the switchover will occur in two stages. ? stage 1: the output will remain low for a limited number of falling edges of clk2. ? stage 2: the output will follow clk2. timing diagram 3
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 12 case #4: input clock failure: switching from the selected clock input stuck in an undetermined state to a valid clock input (rpe-enabled). if clk1 fails to an undetermined state (e.g., amplitude falls below the 100mv (v in ) minimum single-ended input limit, or 200mv differentially) before the rpe mux selects clk2 (using the sel pin), the switchover to the valid clock clk2 will occur either following case #2 or case #3, depending upon the last valid state at the clk1. if the selected input clock fails to a floating, static, or extremely low signal swing, including 0mv, the fsi function will eliminate any metastable condition and guarantee a stable output signal. no ringing and no undetermined state will occur at the output under these conditions. please note that the fsi function will not prevent duty cycle distortions or runt pulses in case of a slowly deteriorating (but still toggling) input signal. due to the fsi function, the propagation delay will depend upon rise and fall time of the input signal and on its amplitude. refer to ?typical operating characteristics? for detailed information. timing diagram 4
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 13 enable output (en) description the enable function is synchronous so that the outputs will be enabled/di sabled when they are already in the low state. this avoids any chance of generating a runt pulse when the device is enabled/disabled as can happen with asynchronous control. disable output(s): 1. en toggles from high-to-low 2. output(s) follow the selected clock input 3. output (clk) goes to a logic low level (/clk goes to a logic high), after next high- to-low transition of the selected input. see timing diagram 5. enable output(s): 1. en toggles from low-to-high. 2. output(s) follow the selected clock after next high-to-low transition of the selected input. see ?timing diagram 5.? timing diagram 5
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 14 power-on reset (por) description the sy89465u includes an internal power-on reset (por) function to ensure that the rpe logic starts- up in a known logic st ate once the power-supply voltage is stable. an external capacitor connected between v cc and the cap pin (pin 12) controls the delay for the power-on reset function. the required capacitor value calculation is based upon the time the system power supply needs to power up to a minimum of 2.3v. the time constant for the internal power-on-reset must be greater than the time required for the power supply to ramp up to a minimum of 2.3v. the following formula describes this relationship: c( f) t (ms) 12(ms/ f) dps ? as an example, if the time required for the system power supply to power up past 2.3v is 12ms, then the required capacitor value on pin 12 would be: c( f) 12ms 12(ms/ f) ? c(f) 1f
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 15 typical operating characteristics v cc = 2.5v, gnd = 0v, v in 400mv, t r / t f 300ps, r l = 50 ? to v cc ?2v; t a = 25c, unless otherwise stated.
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 16 functional characteristics v cc = 2.5v, gnd = 0v, v in 400mv pk , t r /t f 300ps, r l = 100 ? across output pair; t a = 25c, unless otherwise stated.
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 17 single-ended and di fferential swings figure 1a. single-ended voltage swing figure 1b. differential voltage swing input and output stages figure 2a. simplified differential input stage figure 2b. simplified differential output stage
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 18 input interface applications figure 3a. lvpecl interface (dc-coupled) figure 3b. lvpecl interface (ac-coupled) option: may connect v t to v cc figure 3c. cml interface (dc-coupled) figure 3d. cml interface (ac-coupled) figure 3e. lvds interface (dc-coupled)
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 19 lvds output interface applications lvds specifies a small sw ing of 325mv typical, on a nominal 1.20v common mode above ground. the common mode voltage has tight limits to permit large variations in ground between an lvds driver and receiver. also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep emi low. figure 4a. lvds differential measurement figure 4b. lvds common mode measurement related product and su pport documentation part number function data sheet link sy89464u precision lvpecl runt pulse eliminator 2 :1 mux with 1:10 fanout buffer and internal termination www.micrel.com/product-info/products/sy89464u.shtml hbw solutions new products and applications www.micrel.com/product-info/products/solutions.shtml
micrel, inc. sy89465u august 2010 m9999-080510-c hbwhelp@micrel.com or (408) 955-1690 20 package information packages notes: 1. package meets level 2 moisture sensitivity classification. 2. all parts are dry-packed before shipment. 3. exposed pad must be soldered to a ground for proper thermal management. 44-pin qfn micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is believ ed to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specificati ons at any time without notification to the customer. micrel products are not designed or authoriz ed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. li fe support devices or systems are devices or systems that (a ) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to r esult in a significant injury to the user. a purchaser ?s use or sale of micrel products for use in life support appliances, devices or syst ems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2005 micrel, inc.

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